HPES

Scientific description

The field of computer science has recently undergone profound changes due to the emergence of what are known as multi-core processors. Within a single chip, multiple processing units are integrated. This architectural concept enables systems to meet performance requirements while adhering to strict energy consumption constraints. Multicore processors are used in laptops, graphics processing units (GPUs), high-performance computing (HPC) platforms, as well as in embedded systems such as mobile phones. Furthermore, the high-performance, low-power multicore processors developed for embedded systems will soon be used in data centers for high-performance computing. This poses new scientific challenges for architecture, system, and application designers who are dealing with massively parallel computing platforms.

The number of cores on a chip is increasing rapidly. At the same time, memory bandwidth is growing too slowly to deliver the performance these multi-core platforms are expected to achieve. This phenomenon is known as the "memory wall," and there is currently no effective solution for overcoming this limitation. As the number of cores increases, cache coherence also becomes a major challenge.

Energy consumption is also a major challenge because it places significant constraints on the computing platform, regardless of the application domain. The top-ranked machine on the Green500 has an energy efficiency ratio of 2 Gflops per watt. This ratio must be improved by a factor of 30 when considering exascale computing. Multi-core processors can help improve this ratio, but the software stack must also evolve to support this improvement.

Members

• H-P. Charles (CEA-LIST)
• L. Fesquet (TIMA)
• S. Lesecq (CEA-LETI)
• S. Mancini (TIMA)
• N. Marchand (Gipsa)
• J-F. Méhaut (LIG)
• F. Rastello (INRIA)
• E. Rutten (INRIA)
• L. Vincent (postdoc)
• Naweiluo Zhou (Ph.D. student)

In-house seminars

• October 18, 2013: Control for MPSoC architecture
• November 28, 2013: Dynamic compilation for everyone
• January 27, 2014: Hardware NDAP cache for array prefetches
• April 1, 2014: Improving the performance of transactional memory applications on multicore processors
• Extending the Roofline Model Using a Lower Bound on Data Movement

"Compilation Days" Events

• November 12, 2014: Thesis Defense Day, Victor Lomüller's Defense
• September 18, 2015: Thesis Defense Day, Fernando Endo's Defense
• October 1, 2015: Thesis Defense Day (in Saclay), defense by Alexandre Aminot
• December 13–14, 2016: Thesis compilation day, defense by Diogo Sampaio
• October 17–23, 2017: 3rd Grenoble Workshop on Autonomic Computing and Control

Publications

2016

Autonomic Parallelism and Thread Mapping Control on Software Transactional Memory Naweiluo Zhou, Gwenaël Delaval, Bogdan Robu, Eric Rutten, Jean-François Méhaut 13th IEEE International Conference on Autonomic Computing (ICAC 2016), July 2016, Würzburg, Germany. https://hal.archives-ouvertes.fr/hal-01309681

Control of Autonomic Parallelism Adaptation on Software Transactional Memory Naweiluo Zhou, Gwenaël Delaval, Bogdan Robu, Eric Rutten, Jean-François Méhaut 2016 International Conference on High Performance Computing & Simulation (HPCS 2016), July 2016, Innsbruck, Austria. pp. 180–187, 2016, https://hal.archives-ouvertes.fr/hal-01309195

Autonomic Parallelism Adaptation for Software Transactional Memory Naweiluo Zhou, Gwenaël Delaval, Bogdan Robu, Éric Rutten, Jean-François Méhaut Conference on Parallelism, Architecture, and Systems (COMPAS), July 2016, Lorient, France https://hal.inria.fr/hal-01312786

Autonomic Parallelism Adaptation on Software Transactional Memory Naweiluo Zhou, Gwenaël Delaval, Bogdan Robu, Éric Rutten, Jean-François Méhaut [Research Report] RR-8887, Univ. Grenoble Alpes; INRIA Grenoble. 2016, pp. 24 https://hal.inria.fr/hal-01279599v2

Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory, Naweiluo Zhou Distributed, Parallel, and Cluster Computing [cs.DC]. UJF Grenoble-1; INRIA Grenoble, 2016.Englishhttps://hal.archives-ouvertes.fr/tel-01408450

2015

Chadi Al Khatib, Mohamed Gana, Chouki Aktouf, Laurent Fesquet,“A new methodology for implementing a distributed clock management system for low-power design,”HiPEAC 2015 Conference, Workshop on High Performance Embedded Systems, January 19–21, 2015, Amsterdam, Netherlands.

Chadi Al khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet, "A Generic Clock Controller for Low Power Systems: Experimentation on an AXI Bus," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 5–7, 2015, Daejeon, Korea

2014

M. Berekmeri, D. Serrano, S. Bouchenak, N. Marchand, and B. Robu, "A Control Approach for the Performance of Big Data Systems," Vol. 19(1), IFAC World Congress, 2014.

M. Berekmeri, D. Serrano, S. Bouchenak, N. Marchand, and B. Robu, "Application of Monitoring to Ensure the Performance of Big Data Systems," Francophone Conference on Parallel Computing, Architecture, and Systems (ComPAS), 2014

Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné, Suzanne Lesecq, Xuan-Tu Tran, "FIFO-Level-Based Power Management and Its Application to an H.264 Encoder," IECON’14, 40th Annual Conference of the IEEE Industrial Electronics Society, October 30–November 1, 2014, Dallas, TX, USA. Best Presentation Award

Soguy Mak Karé Gueye, N. de Palma, Eric Rutten, Alain Tchana, Nicolas Berthier,“Coordinating Self-Sizing and Self-Repair Managers for Multi-Tier Systems,”Journal of Future Generation of Computer Systems (FCGS), Issue 35, pp. 14–26, 2014, Springer, IECON’14, 40th Annual Conference of the IEEE Industrial Electronics Society, October 30–November 1, 2014, Dallas, TX, USA. BEST Presentation Award.

Luiz Fabrício Góes, Christiane Pousa Ribeiro, Marcio Castro, Jean-François Mehaut, Murray Cole, and Marcelo Cintra.“Automatic Skeleton-Driven Memory Affinity for Transactional Worklist Applications”. International Journal of Parallel Programming (IJPP), vol. 42, no. 2, pp. 365–382, 2014, Springer

Stéphane Mancini,“Closed-Loop Adaptation of Stochastic Preloading in Arrays,” Proceedings of the ComPAS'2014 Conference, Architecture Session, April 23–25, 2014, Neuchâtel, Switzerland

Sylvain Durand, Hatem Zakaria, Laurent Fesquet, Nicolas Marchand,“A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC” in “Advanced Technology under Process Variability Constraints,” Advances in Computer Science: an International Journal (ACSIJ), Volume 3, Issue 1, January 2014 

Stéphane Mancini “Closed-loop adaptation of stochastic preloading in arrays” ComPAS'2014 conference, Architecture Session, Neuchâtel, Switzerland, April 23–25, 2014

Yeter Akgul, Diego Puschini, Suzanne Lesecq, Pascal Benoit, Edith Beigne, Ivan Miro-Panades, Lionel Torres, “Power Management through DVFS and Dynamic Body Biasing in FD-SOI Circuits,” 51st DAC Conference, San Francisco, June 1–5, 2014

Venmugil Elango, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam, and P. Sadayappan “On Characterizing the Data Movement Complexity of Computational DAGs for Parallel Execution” 26th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA '14 June 23–25, 2014

L. Pilla, C. Pousa Ribeiro, P. Coucheney, F. Broquedis, B. Gaujal, P. Navaux, and J.-F. Mehaut. "A Topology-aware Load Balancing Algorithm for Clustered Hierarchical Multi-core Machines." Future Generation of Computing Systems (FGCS), 30(1):191–201, 2014

2013

M. Berekmeri, D. Sarrano, S. Bouchenak, N. Marchand, and B. Robu, "Modeling and Control of MapReduce Systems," French-Language Conference on Parallel Computing, Architecture, and Systems (ComPAS), 2013

Fauzia, Naznin; Elango, Venmugil; Ravishankar, Mahesh; Ramanujam, J.; Rastello, Fabrice; Rountev, Atanas; Pouchet, Louis-Noël; and Sadayappan, P. “Beyond Reuse Distance Analysis: Dynamic Analysis for Characterization of Data Locality Potential” ACM TACO Transaction on Architecture and Code Optimization, December 2013